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74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 04 -- 11 November 2008 Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nA ports to nB ports. nDIR (active LOW) enables data from nB ports to nA ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nA and nB ports by placing them in a high-impedance OFF-state. Pins nA, nOE and nDIR are referenced to VCC(A) and pins nB are referenced to VCC(B). In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A) (except in suspend mode).
2. Features
I 5 V tolerant inputs/outputs for interfacing with 5 V logic I Wide supply voltage range: N 3 V port (VCC(A)): 1.5 V to 3.6 V N 5 V port (VCC(B)): 1.5 V to 5.5 V I CMOS low power consumption I Direct interface with TTL levels I Control inputs voltage range from 2.7 V to 5.5 V I Inputs accept voltages up to 5.5 V I High-impedance outputs when VCC(A) or VCC(B) = 0 V I Complies with JEDEC standard JESD8-B/JESD36 I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
3. Ordering information
Table 1. Ordering information Temperature range -40 C to +125 C Package Name SSOP48 TSSOP48 HUQFN60U Description plastic shrink small outline package; 48 leads; body width 7.5 mm Version SOT370-1 Type number 74ALVC164245DL
74ALVC164245DGG -40 C to +125 C 74ALVC164245BQ -40 C to +125 C
plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm plastic thermal enhanced ultra thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.55 mm SOT1025-1
4. Functional diagram
1DIR 1OE 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7
2DIR 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7
001aaa789
Fig 1.
Logic symbol
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Product data sheet
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74ALVC164245
16-bit dual supply translating transceiver; 3-state
1OE 1DIR 2OE 2DIR
G3 3EN1[BA] 3EN2[AB] G6 6EN1[BA] 6EN2[AB]
1A0
1 2
1B0
1A1 1A2 1A3 1A4 1A5 1A6 1A7 2A0 4 5 2A1 2A2 2A3 2A4 2A5 2A6 2A7
1B1 1B2 1B3 1B4 1B5 1B6 1B7 2B0
2B1 2B2 2B3 2B4 2B5 2B6 2B7
001aaa790
Fig 2.
IEC logic symbol
74ALVC164245_4
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
1DIR 1B0 1B1 GND 1B2 1B3 VCC(B) 1B4 1B5
1 2 3 4 5 6 7 8 9
48 1OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC(A) 41 1A4 40 1A5 39 GND 38 1A6 37 1A7 36 2A0 35 2A1 34 GND 33 2A2 32 2A3 31 VCC(A) 30 2A4 29 2A5 28 GND 27 2A6 26 2A7 25 2OE
001aab037
GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 17 VCC(B) 18 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2DIR 24
74ALVC164245
Fig 3.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
terminal 1 index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B13 B15 B16 B17
A25
A24
A23
A22
74ALVC164245
B14 A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aai851
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4.
Pin configuration SOT1025-1 (HUQFN60U)
74ALVC164245_4
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Product data sheet
Rev. 04 -- 11 November 2008
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 GND VCC(B) 1OE, 2OE 4, 10, 15, 21, 28, 34, 39, 45 7, 18 48, 25 SOT1025-1 A30, A13 B20, A31, D5, D1, A2, B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 A32, A3, A8, A11, A16, A19, A24, A27 A1, A10, A29, A14 B18, A28, D8, D4, A25, B16, B15, A22 A21, B13, B12, A18, D3, D7, A15, B10 A17, A26 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 direction control input data input/output data input/output ground (0 V) supply voltage B (5 V bus) output enable input (active LOW) data input/output data input/output supply voltage A (3 V bus) not connected Description
1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 VCC(A) n.c. 31, 42 -
6. Functional description
Table 3. Inputs nOE L L H
[1]
Function table[1] Outputs nDIR L H X nAn A=B inputs Z nBn inputs B=A Z
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See Table note 1. Symbol VCC(B) VCC(A) IIK VI VI/O IOK VO IO(sink/source) ICC
74ALVC164245_4
Parameter supply voltage B supply voltage A input clamping current input voltage input/output voltage output clamping current output voltage output sink or source current supply current
Conditions VCC(B) VCC(A) VCC(B) VCC(A) VI < 0 V
[2]
Min -0.5 -0.5 -50 -0.5 -0.5 [2] [2]
Max +6.0 +4.6 +6.0 VCC + 0.5 50 VCC + 0.5 +6.0 50 100
Unit V V mA V V mA V V mA mA
VO > VCC or VO < 0 V output HIGH or LOW output 3-state VO = 0 V to VCC
-0.5 -0.5 -
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Product data sheet
Rev. 04 -- 11 November 2008
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See Table note 1. Symbol IGND Tstg Ptot Parameter ground current storage temperature total power dissipation Tamb = -40 C to +125 C (T)SSOP48 package HUQFN60U package
[1] [2] [3] [4]
[3] [4]
Conditions
Min -100 -65 -
Max +150 500 1000
Unit mA C mW mW
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC(B) Recommended operating conditions Parameter supply voltage B Conditions VCC(B) VCC(A) maximum speed performance low-voltage applications VCC(A) supply voltage A VCC(B) VCC(A) maximum speed performance low-voltage applications VI VI/O VO Tamb t/V input voltage input/output voltage output voltage ambient temperature input transition rise and fall rate VCC(A) = 2.7 V to 3.0 V VCC(A) = 3.0 V to 3.6 V VCC(B) = 3.0 V to 4.5 V VCC(B) = 4.5 V to 5.5 V control inputs: nOE and nDIR A port B port A port B port 2.7 1.5 0 0 0 0 0 -40 0 0 0 0 3.6 3.6 5.5 VCC(A) VCC(B) VCC(A) VCC(B) +125 20 10 20 10 V V V V V V V C ns/V ns/V ns/V ns/V 2.7 1.5 5.5 5.5 V V Min Typ Max Unit
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions B port VCC(B) = 3.0 V to 5.5 V A port, nOE and nDIR VCC(A) = 3.0 V to 3.6 V VCC(A) = 2.3 V to 2.7 V VIL LOW-level input voltage B port VCC(B) = 4.5 V to 5.5 V VCC(B) = 3.0 V to 3.6 V A port, nOE and nDIR VCC(A) = 3.0 V to 3.6 V VCC(A) = 2.3 V to 2.7 V VOH HIGH-level B port; VI = VIH or VIL output voltage IO = -24 mA; VCC(B) = 4.5 V IO = -12 mA; VCC(B) = 4.5 V IO = -18 mA; VCC(B) = 3.0 V IO = -100 A; VCC(B) = 3.0 V A port; VI = VIH or VIL IO = -24 mA; VCC(A) = 3.0 V IO = -100 A; VCC(A) = 3.0 V IO = -12 mA; VCC(A) = 2.7 V IO = -8 mA; VCC(A) = 2.3 V IO = -100 A; VCC(A) = 2.3 V VOL LOW-level B port; VI = VIH or VIL output voltage IO = 24 mA; VCC(B) = 4.5 V IO = 12 mA; VCC(B) = 4.5 V IO = 100 A; VCC(B) = 4.5 V IO = 18 mA; VCC(B) = 3.0 V IO = 100 A; VCC(B) = 3.0 V A port; VI = VIH or VIL IO = 24 mA; VCC(A) = 3.0 V IO = 100 A; VCC(A) = 3.0 V IO = 12 mA; VCC(A) = 2.7 V IO = 12 mA; VCC(A) = 2.3 V IO = 100 A; VCC(A) = 2.3 V 0.55 0.20 0.40 0.60 0.20 0.80 V 0.30 V 0.60 V 0.60 V 0.20 V VCC(A) - 0.7 VCC(A) - 0.2 VCC(A) - 0.5 VCC(A) - 0.6 VCC(A) - 1.0 VCC(A) - 0.3 VCC(A) - 0.8 VCC(A) - 0.6 V V V V V
[2] [2] [2] [2] [2]
Tamb = -40 C to +85 C Min 2.0 2.0 1.7 VCC(B) - 0.8 VCC(B) - 0.5 VCC(B) - 0.8 Typ Max 0.8 0.7 0.8 0.7 -
Tamb = -40 C to +125 C Unit Min 2.0 2.0 1.7 VCC(B) - 1.2 VCC(B) - 0.8 VCC(B) - 1.0 Typ Max 0.8 0.7 0.8 0.7 V V V V V V V V V V V
VCC(B) - 0.2 VCC(B)
VCC(B) - 0.3 VCC(B)
VCC(A) - 0.2 VCC(A)
VCC(A) - 0.3 VCC(A)
-
-
0.55 0.40 0.20 0.55 0.20
-
-
0.60 V 0.80 V 0.30 V 0.80 V 0.30 V
74ALVC164245_4
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Product data sheet
Rev. 04 -- 11 November 2008
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOZ ICC ICC CI CI/O input leakage current Conditions VI = 5.5 V or GND
[3]
Tamb = -40 C to +85 C Min [4]
Tamb = -40 C to +125 C Unit Min Typ 0.1 0.1 0.1 5 Max 10 20 80 A A A
Typ 0.1 0.1 0.1 5 4.0 5.0
Max 5 10 40 500 -
OFF-state VI = VIH or VIL; output current VO = VCC or GND supply current VI = VCC or GND; IO = 0 A additional per control pin; supply current VI = VCC - 0.6 V; IO = 0 A input capacitance input/output capacitance A and B port
-
5000 A pF pF
[1] [2] [3] [4]
All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb = 25 C. If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible. For transceivers, the parameter IOZ includes the input leakage current. VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
10. Dynamic characteristics
Table 7. Dynamic characteristics GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter tpd propagation delay Conditions nAn to nBn; see Figure 5 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V nBn to nAn; see Figure 5 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V
[2] [2]
Tamb = -40 C to +85 C
Tamb = -40 C to +125 C
Unit
Min 1.5 1.0 1.0
Typ[1] 3.3 3.0 2.9
Max 7.6 5.9 5.8
Min 1.5 1.0 1.0
Max 9.5 7.5 7.5 ns ns ns
1.0 1.0 1.2
3.0 4.3 2.5
7.6 6.7 5.8
1.0 1.0 1.2
9.5 8.5 7.5
ns ns ns
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Table 7. Dynamic characteristics ...continued GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter ten enable time Conditions nOE to nBn; see Figure 6 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V nOE to nAn; see Figure 6 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V tdis disable time nOE to nBn; see Figure 6 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V nOE to nAn; see Figure 6 VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V tot 3.6 V VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V
[2] [2] [2] [2]
Tamb = -40 C to +85 C
Tamb = -40 C to +125 C
Unit
Min 1.5 1.5 1.0
Typ[1] 4.1 3.6 3.2
Max 11.5 9.2 8.9
Min 1.5 1.5 1.0
Max 14.5 11.5 12.0 ns ns ns
1.5 1.5 1.0
4.6 4.3 3.2
12.3 9.3 8.9
1.5 1.5 1.0
15.5 12.0 11.5
ns ns ns
2.0 2.5 2.1
2.7 4.6 4.9
10.5 9.0 8.6
2.0 2.5 2.1
13.5 11.5 11.0
ns ns ns
1.0 1.5 2.0
2.7 3.5 3.2
9.3 9.0 8.6
1.0 1.5 2.0
12.0 11.5 11.0
ns ns ns
74ALVC164245_4
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Table 7. Dynamic characteristics ...continued GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter CPD power dissipation capacitance Conditions 5 V port: nAn to nBn; VCC(B) = 5 V; VCC(A) = 3.3 V outputs enabled outputs disabled 3 V port: nBn to nAn; VCC(B) = 5 V; VCC(A) = 3.3 V outputs enabled outputs disabled
[1] [2]
[3][4] [3][4]
Tamb = -40 C to +85 C
Tamb = -40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
-
30 15
-
-
-
pF pF
-
40 5
-
-
-
pF pF
All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb = 25 C. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. The condition is VI = GND to VCC.
[3]
[4]
11. AC waveforms
VI nAn, nBn input GND tPHL VOH nBn, nAn output VOL VM
001aaa792
VM
tPLH
Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Input (nAn, nBn) to output (nBn, nAn) propagation delays
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM
outputs disabled
outputs enabled
mna362
Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with output load.
Fig 6. Table 8. Direction
3-state enable and disable times Measurement points Supply voltage VCC(A) VCC(B) 2.3 V to 2.7 V 2.7 V to 3.6 V 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V Input VI VCC(A) 2.7 V 2.7 V 3.0 V VM 1.5 V 1.5 V 1.5 V Output VM VX VOL(B) + 0.3 V VY VOH(B) - 0.3 V 0.8 x VCC(B) VOH(A) - 0.3 V 0.5 x VCC(A) 1.5 V
A port to B port B port to A port A port to B port B port to A port
0.5 x VCC(A) VOL(A) + 0.15 V VOH(A) - 0.15 V 0.5 x VCC(B) 0.2 x VCC(B) 1.5 V VOL(A) + 0.3 V
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance.
Fig 7. Table 9. Direction
Load circuitry for switching times Test data Supply voltage VCC(A) VCC(B) 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.3 V to 2.7 V 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V to 3.6 V Load CL 50 pF 50 pF 50 pF 50 pF RL 500 500 500 500 VEXT tPLH, tPHL open open open open tPZH, tPHZ GND GND GND GND tPZL, tPLZ 2 x VCC 6.0 V 2 x VCC 6.0 V
A port to B port B port to A port A port to B port B port to A port
74ALVC164245_4
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Product data sheet
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
D
E
A X
c y HE vM A
Z 48 25
Q A2 A1 (A 3) Lp 1 bp 24 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 8.
Package outline SOT370-1 (SSOP48)
(c) NXP B.V. 2008. All rights reserved.
74ALVC164245_4
Product data sheet
Rev. 04 -- 11 November 2008
14 of 19
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9.
Package outline SOT362-1 (TSSOP48)
(c) NXP B.V. 2008. All rights reserved.
74ALVC164245_4
Product data sheet
Rev. 04 -- 11 November 2008
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NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
HUQFN60U: plastic thermal enhanced ultra thin quad flat package; no leads 60 terminals; UTLP based; body 4 x 6 x 0.55 mm
D B A
SOT1025-1
terminal 1 index area
E
A
A1
detail X
e2 v w
M M
CAB C e
e1 1/2 e
b
v w
M M
CAB C C
L1 L eR
D2 D6
A11
B8
B10
A16
D3 D7
y1 C
y
A10 B7
A17 B11
e
Eh 1/2 e
B1 A1 B17 A26
e3
e4
terminal 1 index area
D5 D1
A32
B20
B18
A27
Dh
D8 D4
k
X 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.6 A1 0.05 0.00 b 0.35 0.25 D 4.1 3.9 Dh 1.9 1.8 E 6.1 5.9 Eh 3.9 3.8 e 0.5 e1 1 e2 2.5 e3 3
e4 4.5
eR 0.5
k 0.25 0.15
L
L1
v
w 0.05
y 0.08
y1 0.1
0.35 0.125 0.07 0.25 0.025 EUROPEAN PROJECTION
OUTLINE VERSION SOT1025-1
REFERENCES IEC --JEDEC --JEITA ---
ISSUE DATE 07-08-28 07-11-14
Fig 10. Package outline SOT1025-1 (HUQFN60U)
74ALVC164245_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2008
16 of 19
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
13. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date 20081111 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Change notice Supersedes 74ALVC164245_3 74ALVC164245_2 74ALVC164245_1 Document ID 74ALVC164245_4 Modifications: 74ALVC164245_3 74ALVC164245_2 74ALVC164245_1
*
Added type number 74ALVC164245 (HUQFN60U package)
20040914 20040601 19980826
74ALVC164245_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2008
17 of 19
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74ALVC164245_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 11 November 2008
18 of 19
NXP Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2008 Document identifier: 74ALVC164245_4

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